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zynq-clk-for-3.12353dc6c4 · ·
arm: Xilinx Zynq clock changes for v3.12 Just small two changes where the first fixes documentation and the second improves code readability.
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zynq-cleanup-for-3.12b522877b · ·
arm: Xilinx Zynq cleanup patches for v3.12 This branch contains these fixes: - SLCR cleanup - Hotplug cleanup
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zynq-clk-fixes-for-3.1197d58aef · ·
arm: Xilinx Zynq clock fixes for v3.11 - Fix watchdog clock registration - Fix gem clock propagation
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zynq-defconfig-for-3.11c12d82b8 · ·
arm: Xilinx Zynq defconfig changes for v3.11 Enable zynq uartps driver and initrd in defconfig.
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zynq-dt-for-3.1150dbb4cf · ·
arm: Xilinx Zynq dt changes for v3.11 The branch contains: - DT uart handling cleanup - Support for zc706 and zed board - Removal of board compatible string
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zynq-cleanup-for-3.1188cd4e88 · ·
arm: Xilinx Zynq cleanup patches for v3.11 This branch contains two fixes: - Fix zynq smp code - Do not specify init_irq ptr
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zynq-clk-for-3.1197c4e87d · ·
arm: Xilinx Zynq clock changes for v3.11 Change Xilinx Zynq DT clock description which reflects logical abstraction of Zynq's clock tree. - Refactor PLL driver - Use new clock controller driver - Change timer and uart drivers
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