zynq-clk-for-3.12

michal.simek@xilinx.com

353dc6c4 · clk/zynq/pll: Use #defines for fbdiv min/max values · Aug 20, 2013

arm: Xilinx Zynq clock changes for v3.12

Just small two changes where the first fixes
documentation and the second improves
code readability.