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zynq-soc-for-3.203329659d · ·
arm: Xilinx Zynq SoC patches for v3.20 - Enable pincontrol - Simplified SLCR initialization - Setup default ARCH_NR_GPIO
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zynq-dt-for-3.20ab216ac5 · ·
arm: Xilinx Zynq dt patches for v3.20 - Add USB chipidea driver to DT - Add pincontrol - Add aliases node - Fix WDT node
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zynq-dt-fixes-for-3.191643b316 · ·
arm: Xilinx Zynq DT fixes for v3.19 - Add USB chipidea driver to DT
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zynq-cleanup-for-3.192b175186 · ·
arm: Xilinx Zynq cleanup patches for v3.19 - Remove unused file and declaration
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zynq-dt-for-3.197b01abb0 · ·
arm: Xilinx Zynq dt patches for v3.19 - Declare Digilent and vendor - Add Zybo board support - Fix VDMA documentation to be align with the driver
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zynq-dt-fixes-for-3.182329efbb · ·
arm: Xilinx Zynq DT fixes for v3.18 - Fix gem register size - Fix OPP - Add missing references - Trivial cleanup
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zynq-cleanup-for-3.188097171e · ·
arm: Xilinx Zynq cleanup patches for v3.18 - PM support - Fix L2 useless setting
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zynq-dt-for-3.186f752f70 · ·
arm: Xilinx Zynq dt patches for v3.18 - Add eth phys - Add led for zc702 - Various dts cleanups
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zynq-dt-for-3.17-36a3246c0 · ·
arm: Xilinx Zynq dt patches for v3.17 third pull request - Add Adapteva Parallella board/DT - Add SPI nodes - Add CAN nodes - Clean Zynq description
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zynq-dt-for-3.17-2e0a5c552 · ·
arm: Xilinx Zynq dt patches for v3.17 second pull request - Add GPIO and XADC node to dtsi
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zynq-dt-for-3.178fe9346b · ·
arm: Xilinx Zynq dt patches for v3.17 - Document and use new cadence serial binding
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